商品详情

eDP

?4-lane embedded-DisplayPortoutput with each lane running at 1.62Gbps or 2.7Gbps (2-lane configuration alsosupported)

?FHD (1920*1080), WUXGA(1920*1200),QXGA(2048*1536), WQHD(2560*1440), WQXGA(2560*1600) supported

RGB

?24bit RGB interface (LVCMOS, SDR and DDR supported)

LVDS

? 2-channel 6bit or 8bitLVDS interface with 57MHz to 143MHz clock rate (400Mbps to 1Gbps per data pair)

Clock

?19MHz to 100MHz crystal or single-ended clock input(24MHz and 26MHz optimized)

?Built-in 5000ppm SSC generator for EMI suppression

Misc

? SPI interface for chipconfiguration

? I2C interface for chipconfiguration

? Built-in handshakeprotocol with TCON

? I2C-AUX channel forTCON/DPCD/EDID control

? Built-in test pattern

Power

? 1.2V core supply

? 2.5V/3.3V IO supply (RGBinterface IO can be down to 1.8V for power saving)

? Standby power <1mW

?Typical active power <100mW

?QFN-56 (7mm x 7mm) package